awesome-hdl

HDL toolkit

An aggregated list of hardware description languages, simulators, and compilers

Hardware Description Languages

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last commit: about 2 years ago
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Hardware development / HDL doc

IEEE Std 1364-2001Verilog , , ,
IEEE Std 1076-2000VHDL standards
IEEE Std 1666-2011SystemC standards

Hardware development / HDL simulators and compilers / Verilog

VerilatorVerilog to C++ transpiler
Icarus Verilogsimulator
YosysRTL synthesis

Hardware development / HDL simulators and compilers / VHDL

nvc641almost 2 years agoGPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
GHDL2,425almost 2 years agoVHDL compiler and simulator, IEEE 1076-2002, written in ADA

Hardware development / HDL simulators and compilers / chisel/firrtl

essent146about 2 years agofirrtl to optimized C++ transpiler
treadle153about 2 years agofirrtl simulator written in Scala

Hardware development / HDL simulators and compilers

Lola-2

Hardware development / HDL simulators and compilers / Lola-2

Oberon-2013Project Oberon, 2013 Edition, written in

Hardware development / Meta HDL and Transpilers

SystemCan IEEE standard meta-HDL
VisualHDLan integrated development environment (IDE) rapid design for FPGAs
ROHD377almost 2 years agoA framework for hardware description and verification, 2021+
concat439over 2 years agoHaskell to hardware, 2016+
https://github.com/conal/talk-2015-haskell-to-hardware58about 10 years ago
CλaSH1,451almost 2 years agoA functional hardware description language
pipelineDSL1about 5 years agoA Haskell DSL for describing hardware pipelines
Bluespec960almost 2 years agoCompiler, simulator, and tools for the Bluespec Hardware Description Language
sv2v571almost 2 years agoSystemVerilog to Verilog conversion
jhdl..2006
PSHDL
reqack29almost 2 years agoelastic circuit toolchain
hdl-js86almost 8 years agoHardware description language (HDL) parser, and Hardware simulator
shdlSimple Hardware Description Language
Julia-Verilog48over 9 years agoa Verilog-generation DSL for Julia., 2017
Hardcaml677almost 2 years agoAn OCaml library for designing hardware, complete with testing and simulation tools
Verik41over 3 years agoHDL for design and verification. generates SV. UVM
HWT204almost 2 years agoMeta HDL, verification env. IP-core generator, analysis tools, HDL glue
garnet108almost 2 years agoCoarse-Grained Reconfigurable Architecture generator based on magma, 2018+
magma253almost 2 years agoMeta HDL, 2017+
migen1,236almost 2 years agoMeta HDL, 2011+
Amaranth1,592almost 2 years ago(previously nMigen) - A refreshed Python toolbox for building complex digital hardware, 2018+
MyHDL1,052almost 2 years agoProcess based HDL, verification framework included, 2004+
PyropePython-like language supporting "fluid pipelines" and "live flow", 2017+
PyRTL261almost 2 years agoMeta HDL, simulator suitable for research
PyMTL238almost 7 years agoProcess based HDL, verification framework included, 2014+
veriloggen307about 2 years agoPython, Verilog centric meta HDL with HLS like features, 2015-?
Hdl2169almost 2 years agoAnalog HDL in Python
PyHGL40over 3 years agoMeta HDL, three-state event-driven simulation, 2022+
RHDL14over 13 years ago
hoodlum97over 9 years agoMeta HDL, 2016+
kaze194almost 3 years agoMeta HDL, 2019+
calyx503almost 2 years agoIntermediate Language (IL) for Hardware Accelerator Generators, 2020+
SpadeA hardware description language inspired by modern software languages like Rust
chisel4,037almost 2 years agoMeta HDL, 2012+
SpinalHDL1,688almost 2 years agoMeta HDL 2012+
Quokka21over 2 years agoC# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
Veryl544almost 2 years agoAn original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog

Hardware development / HLS

hlslibsac_math, ac_dsp, ac_types
legup2011-2015, LLVM based c->verilog
bambu2003-?, GCC based c->verilog
aughc->verilog, DSP support
https://github.com/utwente-fmtabstract hls, verification libraries
Shang119over 12 years ago2012-2014, LLVM based, c->verilog
xronos0almost 14 years ago2012, java, simple HLS
Potholes10over 12 years ago2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
hls_recurse5about 10 years ago2015-2016 - conversion of recursive fn. for stackless architectures
hg_lvl_syn1over 15 years ago2010, ILP, Force Directed scheduler
abc<2008-?, A System for Sequential Synthesis and Verification
polyphony102almost 2 years ago2015-2017, simple python to hdl
DelayGraph3almost 10 years ago2016, C#, register assignment algorithms
ahaHLS118over 2 years ago2019, An open source high level synthesis (HLS) tool using LLVM
combinatorylogic/soc59over 6 years ago2019, An experimental System-on-Chip with a custom compiler toolchain
Quokka37over 3 years agoC# to HL RTL translator
Vitis380almost 2 years agoLLVM based, made by Xilinx
XLS2020, HLS toolchain from Google

Hardware development / Other HDL languages

act102almost 2 years agoasynchronous circuit/compiler tools
autopiper48almost 11 years ago
Silice1,326almost 2 years agoA language for hardcoding algorithms into FPGA hardware
TL-Verilog2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

Hardware development / Hardware Intermediate Representations

CIRCT2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
coreir101about 4 years ago2016-?, LLVM HW compiler## License
lgraph213almost 2 years ago2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
firrtl731about 2 years ago2016-?, Flexible Intermediate Representation for RTL
LLHD397over 4 years agoLow Level Hardware Description — A foundation for building hardware design tools
SpyDrNet2019+, Framework for parsing and manipulating structural netlists in Python
VLSIR28almost 2 years agoIC Interchange Formats, defined in Google Protobuf SDL

Hardware development / Synthesis tools

vtr-verilog-to-routing1,028almost 2 years ago
yosys3,538almost 2 years agoRTL synthesis framework

Hardware development / Visualization and Documentation generators

bitfield342over 2 years agoJavascript bit field diagram renderer
d3-wave61over 2 years agoJavascript wave graph visualizer for RTL simulations
d3-hwschematic96over 2 years agoJavascript hierarchical schematic visualizer for HDLs
wavedrom3,030over 2 years agoJavascript wave graph visualizer for documentations and sim
netlistsvg648over 2 years agoJavascript schematic visualizer
sphinx-hwt11over 2 years agoPlugin for sphinx documentation generator which adds schematic into html documentation
Visual DebugCustom simulation visualization framework, available within the IDE

Hardware development / HDL parsers

hdlConvertor284about 2 years agoFast (System) Verilog/VHDL parser written as C++ extension for Python
pyVHDLParser82about 2 years agoVHDL parser written in Python
rust_hdl350almost 2 years agoVHDL parser and language server written in Rust
sv-parser412almost 2 years agoIEEE 1800-2017 System Verilog Parser written in Rust
veribleVerible provides a SystemVerilog parser, style-linter, and formatter
slang644almost 2 years agoSystemVerilog compiler and language service
pyverilog645over 2 years agoPython-based Hardware Design Processing Toolkit for Verilog HDL
Surelog373almost 2 years agoSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API

Hardware development / Other Simulation tools

midas98almost 7 years agoFPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
cocotb1,842almost 2 years agoA coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python
osvvm52almost 2 years agoA VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow
uvvm52almost 2 years agoA free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC

Hardware development / Other Design Automation tools

peakrdl106about 2 years agoCSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT
RgGen341almost 2 years agoCode generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
sv-testsTest suite designed to check compliance with the SystemVerilog standard
tbengy49over 2 years agoCode generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
HDLGen88almost 3 years agoTool for processing of embedded Perl or Python scripts in Verilog source code
fusesoc1,217almost 2 years agoPackage manager and a set of build tools for HDL
bender258almost 2 years agoDependency management tool for hardware design projects
hbs1over 2 years agoA lean dependency management and build system for hardware description projects

Hardware development / PSS : Portable test and Stimulus Standard

Accelleraspecification to create a single representation of stimulus and test scenarios
PSS 2.1 LRMPDF Spec
PSSTools OrgPSS releated tools on GitHub. Parsers, editor plugins
Matthew BallancePSS Blog posts:

Hardware development / PSS : Portable test and Stimulus Standard / Matthew Ballance

Automating Bare-Metal Tests with PSS
PSS Fundamentals: Actions, Components, and Test Generation
Declarative Programming and Multi-Core Tests
Relating Actions with Dataflow
Modeling DMA Test Scenarios with PSS
PSS Memory Management Fundamentals
PSS Concurrency and Resources
Interacting with Devices via PSS Registers
Relating Actions with Dataflow Part2 -- Parallelism

Hardware development / PSS : Portable test and Stimulus Standard

PSS CookBook0almost 3 years agoDocumentation for introducing the usage of PSS language

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