awesome-hdl

HDL toolkit

An aggregated list of hardware description languages, simulators, and compilers

Hardware Description Languages

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last commit: about 1 year ago
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Hardware development / HDL doc
IEEE Std 1364-2001 Verilog , , ,
IEEE Std 1076-2000 VHDL standards
IEEE Std 1666-2011 SystemC standards

Hardware development / HDL simulators and compilers / Verilog
Verilator Verilog to C++ transpiler
Icarus Verilog simulator
Yosys RTL synthesis

Hardware development / HDL simulators and compilers / VHDL
nvc 641 11 months ago GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
GHDL 2,425 11 months ago VHDL compiler and simulator, IEEE 1076-2002, written in ADA

Hardware development / HDL simulators and compilers / chisel/firrtl
essent 146 over 1 year ago firrtl to optimized C++ transpiler
treadle 153 about 1 year ago firrtl simulator written in Scala

Hardware development / HDL simulators and compilers
Lola-2

Hardware development / HDL simulators and compilers / Lola-2
Oberon-2013 Project Oberon, 2013 Edition, written in

Hardware development / Meta HDL and Transpilers
SystemC an IEEE standard meta-HDL
VisualHDL an integrated development environment (IDE) rapid design for FPGAs
ROHD 377 11 months ago A framework for hardware description and verification, 2021+
concat 439 over 1 year ago Haskell to hardware, 2016+
https://github.com/conal/talk-2015-haskell-to-hardware 58 over 9 years ago
CλaSH 1,451 11 months ago A functional hardware description language
pipelineDSL 1 over 4 years ago A Haskell DSL for describing hardware pipelines
Bluespec 960 11 months ago Compiler, simulator, and tools for the Bluespec Hardware Description Language
sv2v 571 11 months ago SystemVerilog to Verilog conversion
jhdl ..2006
PSHDL
reqack 29 11 months ago elastic circuit toolchain
hdl-js 86 about 7 years ago Hardware description language (HDL) parser, and Hardware simulator
shdl Simple Hardware Description Language
Julia-Verilog 48 over 8 years ago a Verilog-generation DSL for Julia., 2017
Hardcaml 677 11 months ago An OCaml library for designing hardware, complete with testing and simulation tools
Verik 41 almost 3 years ago HDL for design and verification. generates SV. UVM
HWT 204 11 months ago Meta HDL, verification env. IP-core generator, analysis tools, HDL glue
garnet 108 11 months ago Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+
magma 253 about 1 year ago Meta HDL, 2017+
migen 1,236 about 1 year ago Meta HDL, 2011+
Amaranth 1,592 11 months ago (previously nMigen) - A refreshed Python toolbox for building complex digital hardware, 2018+
MyHDL 1,052 about 1 year ago Process based HDL, verification framework included, 2004+
Pyrope Python-like language supporting "fluid pipelines" and "live flow", 2017+
PyRTL 261 11 months ago Meta HDL, simulator suitable for research
PyMTL 238 about 6 years ago Process based HDL, verification framework included, 2014+
veriloggen 307 about 1 year ago Python, Verilog centric meta HDL with HLS like features, 2015-?
Hdl21 69 11 months ago Analog HDL in Python
PyHGL 40 over 2 years ago Meta HDL, three-state event-driven simulation, 2022+
RHDL 14 over 12 years ago
hoodlum 97 over 8 years ago Meta HDL, 2016+
kaze 194 almost 2 years ago Meta HDL, 2019+
calyx 503 11 months ago Intermediate Language (IL) for Hardware Accelerator Generators, 2020+
Spade A hardware description language inspired by modern software languages like Rust
chisel 4,037 11 months ago Meta HDL, 2012+
SpinalHDL 1,688 11 months ago Meta HDL 2012+
Quokka 21 over 1 year ago C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
Veryl 544 11 months ago An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog

Hardware development / HLS
hlslibs ac_math, ac_dsp, ac_types
legup 2011-2015, LLVM based c->verilog
bambu 2003-?, GCC based c->verilog
augh c->verilog, DSP support
https://github.com/utwente-fmt abstract hls, verification libraries
Shang 119 over 11 years ago 2012-2014, LLVM based, c->verilog
xronos 0 almost 13 years ago 2012, java, simple HLS
Potholes 10 over 11 years ago 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
hls_recurse 5 about 9 years ago 2015-2016 - conversion of recursive fn. for stackless architectures
hg_lvl_syn 1 almost 15 years ago 2010, ILP, Force Directed scheduler
abc <2008-?, A System for Sequential Synthesis and Verification
polyphony 102 12 months ago 2015-2017, simple python to hdl
DelayGraph 3 almost 9 years ago 2016, C#, register assignment algorithms
ahaHLS 118 over 1 year ago 2019, An open source high level synthesis (HLS) tool using LLVM
combinatorylogic/soc 59 almost 6 years ago 2019, An experimental System-on-Chip with a custom compiler toolchain
Quokka 37 almost 3 years ago C# to HL RTL translator
Vitis 380 about 1 year ago LLVM based, made by Xilinx
XLS 2020, HLS toolchain from Google

Hardware development / Other HDL languages
act 102 11 months ago asynchronous circuit/compiler tools
autopiper 48 about 10 years ago
Silice 1,326 11 months ago A language for hardcoding algorithms into FPGA hardware
TL-Verilog 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

Hardware development / Hardware Intermediate Representations
CIRCT 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
coreir 101 over 3 years ago 2016-?, LLVM HW compiler## License
lgraph 213 11 months ago 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
firrtl 731 about 1 year ago 2016-?, Flexible Intermediate Representation for RTL
LLHD 397 over 3 years ago Low Level Hardware Description — A foundation for building hardware design tools
SpyDrNet 2019+, Framework for parsing and manipulating structural netlists in Python
VLSIR 28 11 months ago IC Interchange Formats, defined in Google Protobuf SDL

Hardware development / Synthesis tools
vtr-verilog-to-routing 1,028 11 months ago
yosys 3,538 11 months ago RTL synthesis framework

Hardware development / Visualization and Documentation generators
bitfield 342 over 1 year ago Javascript bit field diagram renderer
d3-wave 61 almost 2 years ago Javascript wave graph visualizer for RTL simulations
d3-hwschematic 96 over 1 year ago Javascript hierarchical schematic visualizer for HDLs
wavedrom 3,030 over 1 year ago Javascript wave graph visualizer for documentations and sim
netlistsvg 648 almost 2 years ago Javascript schematic visualizer
sphinx-hwt 11 over 1 year ago Plugin for sphinx documentation generator which adds schematic into html documentation
Visual Debug Custom simulation visualization framework, available within the IDE

Hardware development / HDL parsers
hdlConvertor 284 about 1 year ago Fast (System) Verilog/VHDL parser written as C++ extension for Python
pyVHDLParser 82 over 1 year ago VHDL parser written in Python
rust_hdl 350 11 months ago VHDL parser and language server written in Rust
sv-parser 412 12 months ago IEEE 1800-2017 System Verilog Parser written in Rust
verible Verible provides a SystemVerilog parser, style-linter, and formatter
slang 644 11 months ago SystemVerilog compiler and language service
pyverilog 645 over 1 year ago Python-based Hardware Design Processing Toolkit for Verilog HDL
Surelog 373 11 months ago SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API

Hardware development / Other Simulation tools
midas 98 almost 6 years ago FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
cocotb 1,842 11 months ago A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python
osvvm 52 11 months ago A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow
uvvm 52 11 months ago A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC

Hardware development / Other Design Automation tools
peakrdl 106 about 1 year ago CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT
RgGen 341 11 months ago Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
sv-tests Test suite designed to check compliance with the SystemVerilog standard
tbengy 49 over 1 year ago Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
HDLGen 88 almost 2 years ago Tool for processing of embedded Perl or Python scripts in Verilog source code
fusesoc 1,217 11 months ago Package manager and a set of build tools for HDL
bender 258 about 1 year ago Dependency management tool for hardware design projects
hbs 1 over 1 year ago A lean dependency management and build system for hardware description projects

Hardware development / PSS : Portable test and Stimulus Standard
Accellera specification to create a single representation of stimulus and test scenarios
PSS 2.1 LRM PDF Spec
PSSTools Org PSS releated tools on GitHub. Parsers, editor plugins
Matthew Ballance PSS Blog posts:

Hardware development / PSS : Portable test and Stimulus Standard / Matthew Ballance
Automating Bare-Metal Tests with PSS
PSS Fundamentals: Actions, Components, and Test Generation
Declarative Programming and Multi-Core Tests
Relating Actions with Dataflow
Modeling DMA Test Scenarios with PSS
PSS Memory Management Fundamentals
PSS Concurrency and Resources
Interacting with Devices via PSS Registers
Relating Actions with Dataflow Part2 -- Parallelism

Hardware development / PSS : Portable test and Stimulus Standard
PSS CookBook 0 almost 2 years ago Documentation for introducing the usage of PSS language

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