awesome-hdl

Hardware Description Languages

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last commit: about 2 months ago
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Hardware development / HDL doc
IEEE Std 1364-2001 Verilog , , ,
IEEE Std 1076-2000 VHDL standards
IEEE Std 1666-2011 SystemC standards

Hardware development / HDL simulators and compilers / Verilog
Verilator Verilog to C++ transpiler
Icarus Verilog simulator
Yosys RTL synthesis

Hardware development / HDL simulators and compilers / VHDL
nvc 632 4 days ago GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
GHDL 2,348 3 days ago VHDL compiler and simulator, IEEE 1076-2002, written in ADA

Hardware development / HDL simulators and compilers / chisel/firrtl
essent 135 4 months ago firrtl to optimized C++ transpiler
treadle 152 about 1 month ago firrtl simulator written in Scala

Hardware development / HDL simulators and compilers
Lola-2

Hardware development / HDL simulators and compilers / Lola-2
Oberon-2013 Project Oberon, 2013 Edition, written in

Hardware development / Meta HDL and Transpilers
SystemC an IEEE standard meta-HDL
VisualHDL an integrated development environment (IDE) rapid design for FPGAs
ROHD 372 17 days ago A framework for hardware description and verification, 2021+
concat 436 7 months ago Haskell to hardware, 2016+
https://github.com/conal/talk-2015-haskell-to-hardware 58 over 8 years ago
CλaSH 1,428 2 days ago A functional hardware description language
pipelineDSL 1 over 3 years ago A Haskell DSL for describing hardware pipelines
Bluespec 938 29 days ago Compiler, simulator, and tools for the Bluespec Hardware Description Language
sv2v 541 6 days ago SystemVerilog to Verilog conversion
jhdl ..2006
PSHDL
reqack 29 over 2 years ago elastic circuit toolchain
hdl-js 85 almost 6 years ago Hardware description language (HDL) parser, and Hardware simulator
shdl Simple Hardware Description Language
Julia-Verilog 47 over 7 years ago a Verilog-generation DSL for Julia., 2017
Hardcaml 650 about 1 month ago An OCaml library for designing hardware, complete with testing and simulation tools
Verik 41 almost 2 years ago HDL for design and verification. generates SV. UVM
HWT 198 4 months ago Meta HDL, verification env. IP-core generator, analysis tools, HDL glue
garnet 106 3 days ago Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+
magma 244 4 months ago Meta HDL, 2017+
migen 1,197 about 1 month ago Meta HDL, 2011+
Amaranth 1,542 15 days ago (previously nMigen) - A refreshed Python toolbox for building complex digital hardware, 2018+
MyHDL 1,034 about 2 months ago Process based HDL, verification framework included, 2004+
Pyrope Python-like language supporting "fluid pipelines" and "live flow", 2017+
PyRTL 254 about 2 months ago Meta HDL, simulator suitable for research
PyMTL 235 almost 5 years ago Process based HDL, verification framework included, 2014+
veriloggen 306 about 2 months ago Python, Verilog centric meta HDL with HLS like features, 2015-?
Hdl21 67 29 days ago Analog HDL in Python
PyHGL 40 over 1 year ago Meta HDL, three-state event-driven simulation, 2022+
RHDL 14 over 11 years ago
hoodlum 96 over 7 years ago Meta HDL, 2016+
kaze 193 11 months ago Meta HDL, 2019+
calyx 486 1 day ago Intermediate Language (IL) for Hardware Accelerator Generators, 2020+
Spade A hardware description language inspired by modern software languages like Rust
chisel 3,937 1 day ago Meta HDL, 2012+
SpinalHDL 1,632 2 days ago Meta HDL 2012+
Quokka 21 4 months ago C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
Veryl 477 11 days ago An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog

Hardware development / HLS
hlslibs ac_math, ac_dsp, ac_types
legup 2011-2015, LLVM based c->verilog
bambu 2003-?, GCC based c->verilog
augh c->verilog, DSP support
https://github.com/utwente-fmt abstract hls, verification libraries
Shang 118 over 10 years ago 2012-2014, LLVM based, c->verilog
xronos 0 almost 12 years ago 2012, java, simple HLS
Potholes 10 over 10 years ago 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
hls_recurse 5 about 8 years ago 2015-2016 - conversion of recursive fn. for stackless architectures
hg_lvl_syn 1 almost 14 years ago 2010, ILP, Force Directed scheduler
abc <2008-?, A System for Sequential Synthesis and Verification
polyphony 101 about 1 month ago 2015-2017, simple python to hdl
DelayGraph 3 almost 8 years ago 2016, C#, register assignment algorithms
ahaHLS 115 4 months ago 2019, An open source high level synthesis (HLS) tool using LLVM
combinatorylogic/soc 59 almost 5 years ago 2019, An experimental System-on-Chip with a custom compiler toolchain
Quokka 36 over 1 year ago C# to HL RTL translator
Vitis 379 8 months ago LLVM based, made by Xilinx
XLS 2020, HLS toolchain from Google

Hardware development / Other HDL languages
act 99 1 day ago asynchronous circuit/compiler tools
autopiper 46 almost 9 years ago
Silice 1,287 25 days ago A language for hardcoding algorithms into FPGA hardware
TL-Verilog 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

Hardware development / Hardware Intermediate Representations
CIRCT 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
coreir 100 over 2 years ago 2016-?, LLVM HW compiler## License
lgraph 204 13 days ago 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
firrtl 720 about 2 months ago 2016-?, Flexible Intermediate Representation for RTL
LLHD 392 over 2 years ago Low Level Hardware Description — A foundation for building hardware design tools
SpyDrNet 2019+, Framework for parsing and manipulating structural netlists in Python
VLSIR 27 about 2 months ago IC Interchange Formats, defined in Google Protobuf SDL

Hardware development / Synthesis tools
vtr-verilog-to-routing 1,003 1 day ago
yosys 3,420 2 days ago RTL synthesis framework

Hardware development / Visualization and Documentation generators
bitfield 335 8 months ago Javascript bit field diagram renderer
d3-wave 58 9 months ago Javascript wave graph visualizer for RTL simulations
d3-hwschematic 93 7 months ago Javascript hierarchical schematic visualizer for HDLs
wavedrom 2,932 6 months ago Javascript wave graph visualizer for documentations and sim
netlistsvg 627 8 months ago Javascript schematic visualizer
sphinx-hwt 11 4 months ago Plugin for sphinx documentation generator which adds schematic into html documentation
Visual Debug Custom simulation visualization framework, available within the IDE

Hardware development / HDL parsers
hdlConvertor 281 about 1 month ago Fast (System) Verilog/VHDL parser written as C++ extension for Python
pyVHDLParser 77 3 months ago VHDL parser written in Python
rust_hdl 332 14 days ago VHDL parser and language server written in Rust
sv-parser 397 2 days ago IEEE 1800-2017 System Verilog Parser written in Rust
verible Verible provides a SystemVerilog parser, style-linter, and formatter
slang 597 1 day ago SystemVerilog compiler and language service
pyverilog 619 4 months ago Python-based Hardware Design Processing Toolkit for Verilog HDL
Surelog 357 1 day ago SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API

Hardware development / Other Simulation tools
midas 96 almost 5 years ago FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
cocotb 1,749 11 days ago A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python
osvvm 49 about 1 month ago A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow
uvvm 49 about 1 month ago A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC

Hardware development / Other Design Automation tools
peakrdl 91 about 1 month ago CSR toolchain to generate RTL, UVM RAL models, docment(html and markdown), IPXACT, c header from SystemRDL or IPXACT
RgGen 319 3 months ago Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
sv-tests Test suite designed to check compliance with the SystemVerilog standard
tbengy 48 5 months ago Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
HDLGen 85 11 months ago Tool for processing of embedded Perl or Python scripts in Verilog source code
fusesoc 1,172 3 days ago Package manager and a set of build tools for HDL
bender 232 about 1 month ago Dependency management tool for hardware design projects
hbs 1 5 months ago A lean dependency management and build system for hardware description projects

Hardware development / PSS : Portable test and Stimulus Standard
Accellera specification to create a single representation of stimulus and test scenarios
PSS 2.1 LRM PDF Spec
PSSTools Org PSS releated tools on GitHub. Parsers, editor plugins
Matthew Ballance PSS Blog posts:

Hardware development / PSS : Portable test and Stimulus Standard / Matthew Ballance
Automating Bare-Metal Tests with PSS
PSS Fundamentals: Actions, Components, and Test Generation
Declarative Programming and Multi-Core Tests
Relating Actions with Dataflow
Modeling DMA Test Scenarios with PSS
PSS Memory Management Fundamentals
PSS Concurrency and Resources
Interacting with Devices via PSS Registers
Relating Actions with Dataflow Part2 -- Parallelism

Hardware development / PSS : Portable test and Stimulus Standard
PSS CookBook 0 11 months ago Documentation for introducing the usage of PSS language

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