clash-compiler
Compiler
A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog.
Haskell to VHDL/Verilog/SystemVerilog compiler
1k stars
54 watching
154 forks
Language: Haskell
last commit: 11 months ago
Linked from 3 awesome lists
asicfpgahardware-description-languagehaskellsystemverilogverilogvhdl
aolofsson/awesome-opensource-hardware
drom/awesome-hdl
uhub/awesome-haskellRelated projects:
| Repository | Description | Stars |
|---|---|---|
 conal/talk-2015-haskell-to-hardware | A compiler project that translates Haskell programs to hardware instructions for parallel processing on reprogrammable devices. | 58 |
 standardsemiconductor/lion | Develops a formally verified RISC-V processor core using Haskell | 249 |
 intel/systemc-compiler | Translates synthesizable SystemC code to synthesizable SystemVerilog. | 256 |
 cfelton/rhea | A collection of MyHDL cores and tools for complex digital circuit design | 85 |
 b-lang-org/bsc | A toolchain for designing and synthesizing digital electronic hardware | 960 |
 zachjs/sv2v | Converts SystemVerilog to Verilog code for hardware design and simulation | 571 |
 ndmitchell/cmdargs | A Haskell library for building command line applications with minimal code | 91 |
 asyncvlsi/act | Asynchronous circuit design and simulation tools using a hardware description language. | 102 |
 vmchale/kempe | A compiled stack-based language with a toy compiler for x86_64 and aarch64 targeting | 58 |
 aucohl/dffram | A compiler for designing and generating layouts of memory compilers using DFF/Latch cells | 137 |
 nic30/hdlconvertor | An ANTLR4-based parser and code generator for SystemVerilog/VHDL | 284 |
 systemrdl/systemrdl-compiler | A compiler front-end for Accellera's SystemRDL 2.0 register description language | 237 |
 g-ford/cradle | Building a compiler in Haskell using a hands-on, top-down approach inspired by the "Let's Build a Compiler" series | 161 |
 cambridgehackers/fpgamake | Generates Makefiles to synthesize and route digital circuits from Verilog designs using Vivado | 93 |
 talw/crisp-compiler | A Haskell compiler for a Lisp/Scheme-inspired language with an LLVM backend | 99 |