sv2v
design converter
Converts SystemVerilog to Verilog code for hardware design and simulation
SystemVerilog to Verilog conversion
561 stars
16 watching
55 forks
Language: Haskell
last commit: 25 days ago
Linked from 2 awesome lists
conversionsystemverilogverilogyosys
aolofsson/awesome-opensource-hardware
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