sv2v

design converter

Converts SystemVerilog to Verilog code for hardware design and simulation

SystemVerilog to Verilog conversion

571 stars

16 watching

55 forks

Language: Haskell

last commit: 4 months ago

Linked from 2 awesome lists

conversionsystemverilogverilogyosys

Backlinks from these awesome lists:

Related projects:

Repository	Description	Stars
clash-lang/clash-compiler	A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog.	1,451
nvlabs/verilog-eval	An evaluation harness for generating Verilog code from natural language prompts	188
dalance/sv-parser	A SystemVerilog parser library for Rust.	412
ddiidev/json2v	Converts JSON data to Vlang structs with customizable structure and type handling.	28
chipsalliance/surelog	Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing	373
eirikpre/vscode-systemverilog	A VS Code extension providing support for SystemVerilog code editing and analysis	130
intel/systemc-compiler	Translates synthesizable SystemC code to synthesizable SystemVerilog.	256
chipsalliance/uhdm	Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions	204
avi-d-coder/implicit-hie	Automates the creation of cabal or stack configuration files for multi-component Haskell projects.	204
chipsalliance/synlig	A SystemVerilog synthesis tool that generates digital circuit designs from HDL code	170
ollix/svg2nvg	Converts SVG files to nanovg source code	49
galacticstudios/kicadverilog	Converts KiCad schematic designs into Verilog code to simulate and design digital circuits	57
kiffie/edc2svd	Converts MCU register descriptions from the EDC format to the SVD format	6
v420v/vas	An x86-64 assembler written in V language	97
interplanetary-robot/verilog.jl	A Verilog generation DSL for Julia.	48