Surelog

chipsalliance/uhdm204

Object model generator

Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions

chipsalliance/verible1.4K

SystemVerilog parser

Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance.

chipsalliance/synlig170

HDL synthesizer

A SystemVerilog synthesis tool that generates digital circuit designs from HDL code

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

chipsalliance/sv-tests302

SystemVerilog tester

A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools.

chipsalliance/cores-veer-el2252

RISC-V processor core

A Verilog RTL design for an EL2 RISC-V core with various peripherals and features

intel/systemc-compiler256

SystemC translator

Translates synthesizable SystemC code to synthesizable SystemVerilog.

pyhdi/pyverilog645

HDL analyzer

Toolkit for analyzing and processing Verilog HDL designs

bensampson5/libsv23

HDL library

A SystemVerilog digital hardware IP library with automated testbenches and continuous integration

zachjs/sv2v571

design converter

Converts SystemVerilog to Verilog code for hardware design and simulation

chipsalliance/riscv-dv1K

RISC-V simulator

An instruction generator for RISC-V processor verification

nic30/hdlconvertor284

VHDL/Verilog parser

An ANTLR4-based parser and code generator for SystemVerilog/VHDL

chipsalliance/aib-phy-hardware128

Interface Bus

Hardware implementation of an interface bus specification

clash-lang/clash-compiler1.5K

Compiler

A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog.

galacticstudios/kicadverilog57

Circuit simulator

Converts KiCad schematic designs into Verilog code to simulate and design digital circuits