libsv

An open source, parameterized SystemVerilog digital hardware IP library

GitHub
22 stars
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4 forks
Language: SystemVerilog
last commit: 4 months ago
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asicasic-librarydigital-designfpgafpga-libraryhardwarehardware-designshardware-librarieshdlipsystemverilogverilog

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libsv.readthedocs.io/en/latest/

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