PoC

Hardware library

Provides VHDL implementations of common hardware functions and a Python-based infrastructure for simulation and synthesis.

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

GitHub

553 stars
58 watching
95 forks
Language: VHDL
last commit: about 4 years ago
Linked from 1 awesome list

alteraasicfpgahardware-designshardware-librarieshardware-moduleslatticeosvvmpoc-librarypythonregression-testingsimulationsynthesistestbenchesuvvmverificationvhdlvlsivunitxilinx

Backlinks from these awesome lists:

Related projects:

Repository Description Stars
nic30/hwtlib A comprehensive hardware abstraction layer providing tools and components for designing and testing digital systems on FPGAs. 35
analogdevicesinc/hdl Analog Devices Inc. provides reference designs and HDL libraries for various FPGA projects 1,536
intel/rohd-hcl A collection of reusable, configurable hardware components developed with ROHD 81
asyncvlsi/act Asynchronous circuit design and simulation tools using a hardware description language. 102
osvvm/osvvm A comprehensive VHDL verification utility library with advanced testing and verification capabilities 228
bensampson5/libsv A SystemVerilog digital hardware IP library with automated testbenches and continuous integration 23
nvdla/hw The NVDLA project provides hardware designs and tools for building deep learning inference accelerators. 1,763
pyhdi/pyverilog Toolkit for analyzing and processing Verilog HDL designs 645
philtomson/rhdl A Ruby language and framework for designing and describing digital hardware systems 14
parallella/parallella-hw Design files and FPGA sources for a supercomputing board with heterogeneous processing cores. 413
aolofsson/oh A comprehensive Verilog library of silicon-proven hardware building blocks for designing ASICs and FPGAs. 1,206
mit-plv/koika A formal language for designing and verifying rule-based hardware systems 143
hdl-util/i2c A SystemVerilog implementation of the Inter-IC bus protocol for FPGAs 23
masc-ucsc/livehd A compiler infrastructure for hardware design optimization and simulation. 213
clash-lang/clash-compiler A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog. 1,451