Cores-VeeR-EH1
RISC-V Core
A RISC-V processor core design implemented in SystemVerilog RTL
VeeR EH1 core
821 stars
58 watching
221 forks
Language: SystemVerilog
last commit: over 1 year ago
Linked from 1 awesome list
ahb-liteasic-designaxi4fpgafusesocopen-source-hardwareprocessorriscrisc-vriscvriscv32rtlveerverilatorwestern-digital
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