verible

SystemVerilog parser

Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

GitHub

1k stars
48 watching
214 forks
Language: C++
last commit: 2 days ago
Linked from 1 awesome list

analysisformatterhacktoberfestlanguage-server-protocollexerlinterlsp-serverparserproductivitystyle-lintersv-lrmsyntax-treesystemverilogsystemverilog-developersystemverilog-parserveribleyacc

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