verible

chipsalliance/surelog373

SystemVerilog processor

Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing

chipsalliance/sv-tests302

SystemVerilog tester

A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools.

chipsalliance/synlig170

HDL synthesizer

A SystemVerilog synthesis tool that generates digital circuit designs from HDL code

chipsalliance/uhdm204

Object model generator

Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

mit-pdos/perennial165

System verifier

A system for verifying correctness of concurrent and crash-safe systems with recovery procedures

verifytests/verify.serilog1

Logging verifier

A tool for verifying Serilog logging behavior in C# applications

mikepopoloski/slang644

Code analyzer

Provides tools and services for compiling, parsing, and analyzing SystemVerilog code

verifytests/verify.brighter2

Command processor verifier

Adds support for verifying a specific command processing framework

dalance/sv-parser412

Parser library

A SystemVerilog parser library for Rust.

vrahli/velisarios28

Fault-tolerant system verifier

A framework for verifying the correctness of Byzantine fault-tolerant distributed systems

intel/systemc-compiler256

SystemC translator

Translates synthesizable SystemC code to synthesizable SystemVerilog.

siliconcompiler/lambdalib23

Digital system framework

A modular hardware abstraction library for designing and implementing complex digital systems

dalance/svlint318

Linter

A systemVerilog linter tool written in Rust.