sv-tests
SystemVerilog tester
A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools.
Test suite designed to check compliance with the SystemVerilog standard.
297 stars
19 watching
75 forks
Language: SystemVerilog
last commit: 7 days ago
Linked from 1 awesome list
compliance-testinghdlrtlsymbiflowsystemverilogverilog
aolofsson/awesome-opensource-hardwareRelated projects:
| Repository | Description | Stars |
|---|---|---|
| chipsalliance/verible | Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. | 1,380 |
| chipsalliance/surelog | Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing | 367 |
| chipsalliance/synlig | A SystemVerilog synthesis tool that generates digital circuit designs from HDL code | 169 |
| chipsalliance/uhdm | Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions | 202 |
| chipsalliance/cores-veer-eh1 | A RISC-V processor core design implemented in SystemVerilog RTL | 821 |
 testing-library/svelte-testing-library | Provides utilities for testing Svelte components with a focus on realistic testing scenarios and good development practices. | 620 |
 verifytests/verify.serilog | A tool for verifying Serilog logging behavior in C# applications | 1 |
 bensampson5/libsv | A SystemVerilog digital hardware IP library with automated testbenches and continuous integration | 23 |
 nvlabs/verilog-eval | An evaluation harness for generating Verilog code from natural language prompts | 179 |
 zachjs/sv2v | Converts SystemVerilog to Verilog code for hardware design and simulation | 561 |
| chipsalliance/riscv-dv | An instruction generator for RISC-V processor verification | 1,020 |
 vunit/vunit | Automates testing of HDL code through unit tests and testbenches | 742 |
 eirikpre/vscode-systemverilog | A VS Code extension providing support for SystemVerilog code editing and analysis | 127 |
 osvvm/osvvm | A comprehensive VHDL verification utility library with advanced testing and verification capabilities | 225 |
| osvvm/osvvmlibraries | Provides reusable and modular VHDL verification components for creating testbenches and verifying digital circuits. | 51 |