sv-tests

chipsalliance/verible1.4K

SystemVerilog parser

Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance.

chipsalliance/surelog373

SystemVerilog processor

Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing

chipsalliance/synlig170

HDL synthesizer

A SystemVerilog synthesis tool that generates digital circuit designs from HDL code

chipsalliance/uhdm204

Object model generator

Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

testing-library/svelte-testing-library623

Component tester

Provides utilities for testing Svelte components with a focus on realistic testing scenarios and good development practices.

verifytests/verify.serilog1

Logging verifier

A tool for verifying Serilog logging behavior in C# applications

bensampson5/libsv23

HDL library

A SystemVerilog digital hardware IP library with automated testbenches and continuous integration

nvlabs/verilog-eval188

Code generator

An evaluation harness for generating Verilog code from natural language prompts

zachjs/sv2v571

design converter

Converts SystemVerilog to Verilog code for hardware design and simulation

chipsalliance/riscv-dv1K

RISC-V simulator

An instruction generator for RISC-V processor verification

vunit/vunit750

HDL tester

Automates testing of HDL code through unit tests and testbenches

eirikpre/vscode-systemverilog130

SystemVerilog editor

A VS Code extension providing support for SystemVerilog code editing and analysis

osvvm/osvvm228

VHDL verification library

A comprehensive VHDL verification utility library with advanced testing and verification capabilities

osvvm/osvvmlibraries52

Verification framework

Provides reusable and modular VHDL verification components for creating testbenches and verifying digital circuits.