UHDM
Object model generator
Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
204 stars
20 watching
40 forks
Language: C++
last commit: almost 2 years agoLinked from 1 awesome list
ieee-standardlistenerserializationsystemverilogvpi-apivpi-interface
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