UHDM

chipsalliance/surelog373

SystemVerilog processor

Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing

chipsalliance/verible1.4K

SystemVerilog parser

Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance.

chipsalliance/synlig170

HDL synthesizer

A SystemVerilog synthesis tool that generates digital circuit designs from HDL code

verigood-ml/public52

Hardware generator

Translates ONNX models to Verilog-based hardware implementations

wyvernsemi/pcievhost86

PCIe simulator

Generates PCIe traffic and supports logic simulation environments

chipsalliance/sv-tests302

SystemVerilog tester

A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools.

intel/systemc-compiler256

SystemC translator

Translates synthesizable SystemC code to synthesizable SystemVerilog.

zachjs/sv2v571

design converter

Converts SystemVerilog to Verilog code for hardware design and simulation

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

osvvm/osvvm228

VHDL verification library

A comprehensive VHDL verification utility library with advanced testing and verification capabilities

galacticstudios/kicadverilog57

Circuit simulator

Converts KiCad schematic designs into Verilog code to simulate and design digital circuits

chipsalliance/aib-phy-hardware128

Interface Bus

Hardware implementation of an interface bus specification

asyncvlsi/act102

Circuit simulator

Asynchronous circuit design and simulation tools using a hardware description language.

mxmxmx/o_c474

CV generator

Generates CV signals based on user input and stores them in a polymorphic format

ros2/rosidl83

Interface generator

Provides a set of tools and libraries to generate and work with ROS 2 interface definitions and code from IDL files.