public
Hardware generator
Translates ONNX models to Verilog-based hardware implementations
52 stars
2 watching
11 forks
Language: Verilog
last commit: almost 2 years ago
Linked from 1 awesome list
Related projects:
| Repository | Description | Stars |
|---|---|---|
| | A framework that allows designing hardware using Python, providing high-level abstractions for efficient domain-specific languages and tools. | 307 |
| | Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions | 204 |
| | An evaluation harness for generating Verilog code from natural language prompts | 188 |
| | Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design | 43 |
| | A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code. | 132 |
| | A toolset for generating and simulating hardware designs with Python | 204 |
| | Hardware implementation of an interface bus specification | 128 |
| | Toolkit for analyzing and processing Verilog HDL designs | 645 |
| | An ANTLR4-based parser and code generator for SystemVerilog/VHDL | 284 |
| | Converts SystemVerilog to Verilog code for hardware design and simulation | 571 |
| | A Haskell-based DSL for generating Ethereum Virtual Machine (EVM) bytecode | 66 |
| | A Verilog generation DSL for Julia. | 48 |
| | A Python-based framework for building and testing hierarchical hardware models at multiple levels of abstraction. | 238 |
| | Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing | 373 |
| | Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. | 1,403 |