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cv32e40s

by openhwgroup

SystemVerilogpushed almost 2 years ago

4 stage, in-order, secure RISC-V core based on the CV32E40P

AI summary

RISC-V core

A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities

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View on GitHubdocs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest

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