cv32e40s
RISC-V core
A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities
4 stage, in-order, secure RISC-V core based on the CV32E40P
133 stars
17 watching
23 forks
Language: SystemVerilog
last commit: almost 2 years agoLinked from 1 awesome list
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