riscv-openocd
RISC-V debugger
A fork of OpenOCD with RISC-V microcontroller support
Fork of OpenOCD that has RISC-V microcontroller support
34 stars
6 watching
23 forks
Language: C
last commit: 5 months ago Related projects:
Repository | Description | Stars |
---|---|---|
arduino/openocd | Tools for on-chip programming and debugging of embedded systems | 126 |
riscv-rust/gd32vf103-pac | A peripheral access crate for a specific microcontroller family | 36 |
openhwgroup/cv32e40x | A 4-stage RISC-V core for compute-intensive applications with a general-purpose extension interface | 213 |
ve3wwg/stm32f103c8t6 | Provides a development environment for working with the STM32F103 microcontroller | 327 |
riscv-rust/gd32vf103xx-hal | A hardware abstraction layer for the GD32VF103 microcontroller family | 54 |
riscv-rust/e310x | A collection of Rust crates providing peripheral access and hardware abstraction layers for RISC-V based E310x microcontrollers. | 18 |
openhwgroup/cv32e40s | A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities | 131 |
cnlohr/mini-rv32ima | A tiny RISC-V emulator for running Linux-like systems on small devices. | 1,687 |
mrlsd/riscv-fs | A F# implementation of the RISC-V Instruction Set Architecture | 282 |
sergev/litebsd | An operating system for microcontrollers with compact memory footprint and paging support | 308 |
lowrisc/muntjac | A minimal 64-bit RISC-V multicore processor designed to be easy to understand and extend for educational and academic purposes. | 78 |
xmc-rs/xmc4800 | A Rust library for interfacing with the XMC4800 microcontroller peripheral interface | 3 |
b224hisl/rioschip | A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing. | 32 |
chipsalliance/riscv-dv | An instruction generator for RISC-V processor verification | 1,020 |
lekkit/rvvm | An emulator and virtual machine for the RISC-V instruction set architecture. | 936 |