cve2

RISC-V core

A 32-bit RISC-V CPU core with a two-stage pipeline designed for low-cost embedded control applications.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

GitHub

29 stars
7 watching
26 forks
Language: SystemVerilog
last commit: about 2 years ago
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