lion
RISC-V core
Develops a formally verified RISC-V processor core using Haskell
Where Lions Roam: RISC-V on the VELDT
249 stars
12 watching
16 forks
Language: Haskell
last commit: 4 months ago clashhaskellrisc-vveldt
Related projects:
| Repository | Description | Stars |
|---|---|---|
 clash-lang/clash-compiler | A compiler that converts Haskell code into hardware description languages (VHDL, Verilog, SystemVerilog) for digital circuit design and synthesis. | 1,442 |
 chipsalliance/cores-veer-eh1 | A RISC-V processor core design implemented in SystemVerilog RTL | 822 |
 mit-plv/riscv-semantics | A formal specification of the RISC-V instruction set architecture in Haskell | 156 |
| chipsalliance/cores-veer-el2 | A Verilog RTL design for an EL2 RISC-V core with various peripherals and features | 250 |
 black-parrot/black-parrot | A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications. | 626 |
 openhwgroup/core-v-verif | Functional verification project for RISC-V cores | 448 |
 ucsd-progsys/liquidhaskell | A tool for verifying and validating Haskell programs using refinement types and SMT logic | 1,196 |
 commercialhaskell/rio | A standard library for Haskell to provide a common foundation for production software development | 843 |
 cornell-brg/lizard | A modular RISC-V processor design built with Python | 84 |
 olofk/serv | An award-winning RISC-V CPU designed for low-power and area-efficient designs | 1,445 |
 serras/hinc | A Haskell code transpiler from another syntax to the standard Haskell syntax | 111 |
 gsmecher/minimax | An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path | 204 |
 jmorag/mcc | Compiles the MicroC programming language into machine code using Haskell | 116 |
 mrcjkb/haskell-tools.nvim | Provides additional tools and features for Haskell development in Neovim. | 480 |
 symbioticeda/riscv-formal | A framework for formally verifying RISC-V processors by providing a processor-independent formal description and testbenches. | 585 |