lizard

cornell-brg/pymtl3-net43

OCN generator

Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design

cornell-brg/pymtl238

Hardware modeling framework

A Python-based framework for building and testing hierarchical hardware models at multiple levels of abstraction.

moonbaseotago/vroom481

RISC-V CPU

An open-source RISC-V CPU implementation with high performance and multithreading capabilities.

standardsemiconductor/lion249

RISC-V core

Develops a formally verified RISC-V processor core using Haskell

black-parrot/black-parrot634

RISC-V core

A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications.

chipsalliance/riscv-dv1K

RISC-V simulator

An instruction generator for RISC-V processor verification

ronsor/riscv-zig48

CPU emulator

A RISC-V CPU emulator written in Zig.

b224hisl/rioschip33

RISC-V processor

A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing.

knighton/torchplus9

Sequence processor

Enhances PyTorch modules by adding sequence step layers with implicit parentheses and supports custom activation functions.

openhwgroup/cvw282

RISC-V processor core

A configurable RISC-V processor core with various extensions and peripherals

olofk/serv1.5K

RISC-V CPU

An award-winning RISC-V CPU designed for low-power and area-efficient designs

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

chipsalliance/cores-veer-el2252

RISC-V processor core

A Verilog RTL design for an EL2 RISC-V core with various peripherals and features

pyos/dg575

bytecode compiler

A programming language compiler for CPython bytecode

gsmecher/minimax205

RISC-V CPU

An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path