lizard

RISC-V processor

A modular RISC-V processor design built with Python

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

GitHub
84 stars
15 watching
12 forks
Language: Python
last commit: over 5 years ago
Linked from 1 awesome list


Backlinks from these awesome lists:

Related projects:

Repository Description Stars
cornell-brg/pymtl3-net Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design 43
cornell-brg/pymtl A Python-based framework for building and testing hierarchical hardware models at multiple levels of abstraction. 238
moonbaseotago/vroom A high-performance RISC-V CPU implementation for cloud computing 480
standardsemiconductor/lion Develops a formally verified RISC-V processor core using Haskell 249
black-parrot/black-parrot A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications. 629
chipsalliance/riscv-dv An instruction generator for RISC-V processor verification 1,031
ronsor/riscv-zig A RISC-V CPU emulator written in Zig. 48
b224hisl/rioschip A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing. 33
knighton/torchplus Enhances PyTorch modules by adding sequence step layers with implicit parentheses and supports custom activation functions. 9
openhwgroup/cvw A configurable RISC-V processor core with various extensions and peripherals 272
olofk/serv An award-winning RISC-V CPU designed for low-power and area-efficient designs 1,450
chipsalliance/cores-veer-eh1 A RISC-V processor core design implemented in SystemVerilog RTL 824
chipsalliance/cores-veer-el2 A Verilog RTL design for an EL2 RISC-V core with various peripherals and features 250
pyos/dg A programming language compiler for CPython bytecode 576
gsmecher/minimax An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path 205