vroom

ronsor/riscv-zig48

CPU emulator

A RISC-V CPU emulator written in Zig.

b224hisl/rioschip33

RISC-V processor

A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing.

lowrisc/muntjac79

RISC-V processor

A minimal 64-bit RISC-V multicore processor designed to be easy to understand and extend for educational and academic purposes.

lekkit/rvvm953

RISC-V VM

An emulator and virtual machine for the RISC-V instruction set architecture.

gsmecher/minimax205

RISC-V CPU

An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path

cornell-brg/lizard84

RISC-V processor

A modular RISC-V processor design built with Python

black-parrot/black-parrot634

RISC-V core

A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications.

mariusmm/risc-v-tlm285

RISC-V simulator

A RISC-V processor simulator with SystemC and TLM-2 support for various instruction sets and peripherals.

olofk/serv1.5K

RISC-V CPU

An award-winning RISC-V CPU designed for low-power and area-efficient designs

chipsalliance/dromajo219

Emulator

An emulator designed to run RISC-V RV64GC code on RTL co-simulation hardware

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

chipsalliance/cores-veer-el2252

RISC-V processor core

A Verilog RTL design for an EL2 RISC-V core with various peripherals and features

dkogan/vnlog161

Data processor

A toolkit for manipulating tabular ASCII data with normal UNIX tools.

riscv/sail-riscv480

RISC-V spec

A comprehensive formal specification of a RISC-V processor architecture using the Sail language

chipsalliance/riscv-dv1K

RISC-V simulator

An instruction generator for RISC-V processor verification