riscv-formal

RISC-V Verifier

A framework for formally verifying RISC-V processors by providing a processor-independent formal description and testbenches.

RISC-V Formal Verification Framework

GitHub

588 stars
39 watching
99 forks
Language: Verilog
last commit: over 2 years ago
Linked from 1 awesome list


Backlinks from these awesome lists:

Related projects:

Repository Description Stars
openhwgroup/core-v-verif Functional verification project for RISC-V cores 450
mit-pdos/perennial A system for verifying correctness of concurrent and crash-safe systems with recovery procedures 165
mit-plv/riscv-semantics A formal specification of the RISC-V instruction set architecture in Haskell 155
chipsalliance/riscv-dv An instruction generator for RISC-V processor verification 1,031
b224hisl/rioschip A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing. 33
rust-embedded/riscv Provides a set of Rust libraries and tools for accessing and interacting with RISC-V microcontrollers. 855
standardsemiconductor/lion Develops a formally verified RISC-V processor core using Haskell 249
valida-xyz/valida A STARK-based virtual machine designed to improve code reuse, performance and modularity through a custom instruction set, compiler and extensibility features. 296
sifive/prockami Formal verification and implementation of RISC-V processor designs using Coq. 22
chipsalliance/cores-veer-eh1 A RISC-V processor core design implemented in SystemVerilog RTL 824
osvvm/osvvmlibraries Provides reusable and modular VHDL verification components for creating testbenches and verifying digital circuits. 52
risc0/risc0 A platform for executing and verifying computations in a secure, programmable virtual machine. 1,699
riscv-mcu/riscv-openocd A fork of OpenOCD with RISC-V microcontroller support 35
openhwgroup/cv32e40s A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities 131
riscv-rust/gd32vf103-pac A peripheral access crate for a specific microcontroller family 36