risc0
Virtual Machine
A platform for executing and verifying computations in a secure, programmable virtual machine.
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
2k stars
50 watching
428 forks
Language: C++
last commit: 3 days ago cryptographyrisc-vruststarkvirtual-machinezero-knowledge
Related projects:
| Repository | Description | Stars |
|---|---|---|
 0xpolygonmiden/miden-vm | A STARK-based virtual machine designed to execute programs and generate proof of execution without revealing program details. | 631 |
 zerovm/zerovm | An open-source virtual machine project enabling 64-bit x86 application execution in a 32-bit address space. | 817 |
 openhwgroup/cv32e40s | A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities | 131 |
 b224hisl/rioschip | A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing. | 32 |
| risc0/zeth | A system that uses ZK proof to validate Ethereum blocks without relying on validators or sync committees. | 381 |
 black-parrot/black-parrot | A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications. | 626 |
 lekkit/rvvm | An emulator and virtual machine for the RISC-V instruction set architecture. | 936 |
 rust-embedded/riscv | Provides a set of Rust libraries and tools for accessing and interacting with RISC-V microcontrollers. | 852 |
 lowrisc/muntjac | A minimal 64-bit RISC-V multicore processor designed to be easy to understand and extend for educational and academic purposes. | 78 |
 riscv-rust/e310x | A collection of Rust crates providing peripheral access and hardware abstraction layers for RISC-V based E310x microcontrollers. | 18 |
 mariusmm/risc-v-tlm | A RISC-V processor simulator with SystemC and TLM-2 support for various instruction sets and peripherals. | 276 |
| openhwgroup/cv32e40x | A 4-stage RISC-V core for compute-intensive applications with a general-purpose extension interface | 213 |
 moonbaseotago/vroom | A high-performance RISC-V CPU implementation designed for cloud servers | 479 |
 ronsor/riscv-zig | A RISC-V CPU emulator written in Zig. | 48 |
 gsmecher/minimax | An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path | 204 |