veryl

Hardware designer tool

A hardware description language designed to be optimized and easy to use, aiming to simplify the design process

Veryl: A Modern Hardware Description Language

GitHub

544 stars
13 watching
27 forks
Language: Rust
last commit: about 1 month ago
Linked from 2 awesome lists

hdlrtlrustsystemverilogverilog

Backlinks from these awesome lists:

Related projects:

Repository Description Stars
nickmqb/wyre A tool for designing and implementing digital hardware using a concise, typed language that compiles to Verilog 106
philtomson/rhdl A Ruby language and framework for designing and describing digital hardware systems 14
videolang/video A DSL for describing videos in the Racket programming language 137
blarney-lang/blarney A Haskell library for creating hardware descriptions using a functional programming style 98
vhdl-ls/rust_hdl A fast VHDL language server and analysis library written in Rust. 350
willtim/expresso A minimal statically-typed functional programming language designed to be extensible and embeddable. 302
tcr/hoodlum A Rust-based HDL compiler targeting FPGA design and development 97
nadrieril/dhall-rust An implementation of Dhall, a programmable configuration language, in Rust. 306
p12ngh/pipelinedsl A Haskell-based DSL for describing hardware pipelines 1
chaseruskin/legohdl A package manager and development tool for Hardware Description Languages (HDL) used to manage digital designs and intellectual property. 14
sealmove/binarylang A language for building binary parsers and encoders through a syntax-based DSL approach. 59
jwaldrip/admiral.cr A DSL for writing command line interfaces in Crystal 138
toml-rs/toml Tools and utilities for parsing and editing TOML configuration files in Rust 739
ms-ati/docile Simplifies the creation of Domain Specific Languages (DSLs) in Ruby by providing a way to treat methods as a DSL and handle code extraction with local variable access 418
clash-lang/clash-compiler A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog. 1,451