hdlConvertor
VHDL/Verilog parser
An ANTLR4-based parser and code generator for SystemVerilog/VHDL
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
284 stars
23 watching
68 forks
Language: C++
last commit: 6 months ago
Linked from 3 awesome lists
antrl4fpgaparserpythonsystemverilogsystemverilog-parserverilogverilog-parservhdlvhdl-parser
aolofsson/awesome-opensource-hardware
drom/awesome-hdl
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