nvc

VHDL simulator

A VHDL compiler and simulator that translates VHDL code into native machine code for simulation purposes.

VHDL compiler and simulator

GitHub

641 stars

41 watching

83 forks

Language: VHDL

last commit: 2 months ago

Linked from 2 awesome lists

compilerfpgasimulatorvhdl

www.nickg.me.uk/nvc/

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