Surelog
SystemVerilog processor
Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
369 stars
27 watching
69 forks
Language: C++
last commit: 9 days ago
Linked from 3 awesome lists
antlrantlr4-grammarelaborationlinterparserparser-astpreprocessorpython-apisystemveriloguvmverilogvpivpi-apivpi-standard
aolofsson/awesome-opensource-hardware
drom/awesome-hdl
ben-marshall/awesome-open-hardware-verificationRelated projects:
| Repository | Description | Stars |
|---|---|---|
| chipsalliance/uhdm | Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions | 202 |
| chipsalliance/verible | Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. | 1,384 |
| chipsalliance/synlig | A SystemVerilog synthesis tool that generates digital circuit designs from HDL code | 170 |
| chipsalliance/cores-veer-eh1 | A RISC-V processor core design implemented in SystemVerilog RTL | 822 |
| chipsalliance/sv-tests | A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools. | 297 |
| chipsalliance/cores-veer-el2 | A Verilog RTL design for an EL2 RISC-V core with various peripherals and features | 250 |
 intel/systemc-compiler | Translates SystemC code to synthesizable SystemVerilog for hardware design and synthesis. | 250 |
 pyhdi/pyverilog | Toolkit for analyzing and processing Verilog HDL designs | 640 |
 bensampson5/libsv | A SystemVerilog digital hardware IP library with automated testbenches and continuous integration | 23 |
 zachjs/sv2v | Converts SystemVerilog to Verilog code for hardware design and simulation | 564 |
| chipsalliance/riscv-dv | An instruction generator for RISC-V processor verification | 1,027 |
 nic30/hdlconvertor | An ANTLR4-based parser and code generator for SystemVerilog/VHDL | 281 |
| chipsalliance/aib-phy-hardware | Hardware implementation of an interface bus specification | 127 |
 clash-lang/clash-compiler | A compiler that converts Haskell code into hardware description languages (VHDL, Verilog, SystemVerilog) for digital circuit design and synthesis. | 1,442 |
 galacticstudios/kicadverilog | Converts KiCad schematic designs into Verilog code to simulate and design digital circuits | 54 |