Pyverilog
HDL analyzer
Toolkit for analyzing and processing Verilog HDL designs
Python-based Hardware Design Processing Toolkit for Verilog HDL
640 stars
45 watching
180 forks
Language: Python
last commit: 5 months ago
Linked from 2 awesome lists
code-generatorcompilercontrol-flow-analyzerdataflow-analyzerhardwareparserpythonverilog-hdl
aolofsson/awesome-opensource-hardware
drom/awesome-hdlRelated projects:
| Repository | Description | Stars |
|---|---|---|
 paebbels/pyvhdlparser | Parses VHDL source code into a structured representation for analysis and further processing | 81 |
| pyhdi/veriloggen | A framework that allows designing hardware using Python, providing high-level abstractions for efficient domain-specific languages and tools. | 305 |
 nic30/hdlconvertor | An ANTLR4-based parser and code generator for SystemVerilog/VHDL | 281 |
 myhdl/myhdl | An open-source package for using Python as a hardware description and verification language | 1,048 |
 chaseruskin/legohdl | A package manager and development tool for Hardware Description Languages (HDL) used to manage digital designs and intellectual property. | 14 |
 wilsonchen003/hdlgen | Automates HDL generation from embedded scripts in Verilog source code | 87 |
| nic30/hwtlib | A comprehensive hardware abstraction layer providing tools and components for designing and testing digital systems on FPGAs. | 34 |
 kevinpt/symbolator | Tool to visually represent HDL source files as diagrams | 185 |
 dan-fritchman/hdl21 | A hardware description library for analog and custom integrated circuits using Python | 69 |
| nic30/hwt | A toolset for generating and simulating hardware designs with Python | 202 |
 virtuald/pyhcl | A Python parser for HashiCorp Configuration Language | 336 |
 symbiflow/sphinxcontrib-hdl-diagrams | Automates the creation of diagrams from HDL source files | 55 |
 vhdl-ls/rust_hdl | A fast VHDL language server and analysis library written in Rust. | 346 |
 analogdevicesinc/hdl | Analog Devices Inc. provides reference designs and HDL libraries for various FPGA projects | 1,533 |
 vlsi-eda/poc | Provides VHDL implementations of common hardware functions and a Python-based infrastructure for simulation and synthesis. | 551 |