OpenROAD
RTL designer
An RTL-to-GDSII flow tool for rapid semiconductor digital design
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
2k stars
54 watching
566 forks
Language: Verilog
last commit: 4 days ago
Linked from 1 awesome list
cppdefedagdsiilefopendb-databaseopenroadrtltcltiming-analysisverilog
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