RDF-2020
Design Flow
Provides a robust design flow for integrating and preserving research codes in RTL-to-GDS IC implementation
13 stars
1 watching
4 forks
Language: Verilog
last commit: almost 3 years ago
Linked from 1 awesome list
aolofsson/awesome-opensource-hardwareRelated projects:
| Repository | Description | Stars |
|---|---|---|
 the-openroad-project/openroad | An RTL-to-GDSII flow implementation for rapid digital design exploration and physical design implementation. | 1,601 |
| the-openroad-project/openroad-flow-scripts | Automates the process of designing and manufacturing digital electronic systems from RTL to physical GDSII files | 342 |
 rtimothyedwards/qflow | A digital synthesis flow for ASIC design automation, providing a standardized toolchain and configuration files for various tools. | 194 |
 verilog-to-routing/vtr-verilog-to-routing | A CAD flow that takes Verilog descriptions and generates routing information for FPGA design | 1,016 |
 royalicing/syrup | A library that simplifies asynchronous data flow in Swift using enums and Grand Central Dispatch | 2 |
 gdsfactory/gdsfactory | A Python library for designing and verifying complex electronic systems | 542 |
 steveorevo/node-red-contrib-actionflows | Provides a set of nodes to enable extensible and customizable flow design in Node-RED. | 45 |
 intel/rohd | A framework for designing and verifying digital hardware using the Dart programming language | 376 |
 bespoke-silicon-group/bsg_pipeclean_suite | A collection of Verilog designs for stress testing new CAD flows with increasing complexity | 10 |
 clash-lang/clash-compiler | A compiler that transforms high-level Haskell descriptions into synthesizable hardware descriptions. | 1,442 |
 swirrl/grafter | Tools and functions for working with linked data, allowing developers to process and manipulate RDF data. | 190 |
 roytornado/flow-ios | A design pattern and utility library for writing clean and readable asynchronous code in Swift. | 21 |
 man-group/mdf | A toolkit for expressing programs as directed acyclic graphs and wiring together computations over time-series data. | 169 |
 princetonuniversity/opdb | A collection of design benchmarks and instances for evaluating and presenting digital circuit designs | 22 |
 wintechis/flex-rml | A tool for efficient data transformation and knowledge graph construction using RDF Mapping Language | 4 |