vtr-verilog-to-routing
FPGA design router
A CAD flow that takes Verilog descriptions and generates routing information for FPGA design
Verilog to Routing -- Open Source CAD Flow for FPGA Research
1k stars
67 watching
395 forks
Language: C++
last commit: almost 2 years agoLinked from 2 awesome lists
cadedafpgaplacementroutingsynthesisverilogvprvtr
aolofsson/awesome-opensource-hardware
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