vtr-verilog-to-routing
FPGA design router
A CAD flow that takes Verilog descriptions and generates routing information for FPGA design
Verilog to Routing -- Open Source CAD Flow for FPGA Research
1k stars
67 watching
395 forks
Language: C++
last commit: 4 months ago
Linked from 2 awesome lists
cadedafpgaplacementroutingsynthesisverilogvprvtr
aolofsson/awesome-opensource-hardware
drom/awesome-hdlRelated projects:
| Repository | Description | Stars |
|---|---|---|
 pascalkuthe/openvaf | A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code. | 132 |
 veliovgroup/flow-router | A package that extends and improves the performance of Meteor's routing system | 201 |
 iedmrc/vroom-distance | A C++14 optimization engine for solving real-life vehicle routing problems efficiently within a small computing time | 1 |
 ieee-ceda-datc/rdf-2020 | Provides a robust design flow for integrating and preserving research codes in RTL-to-GDS IC implementation | 13 |
 pconst/basic_verilog | A collection of synthesizable Verilog modules useful for FPGA projects | 1,671 |
 vroom-project/vroom | An optimization engine for solving various types of vehicle routing problems with fast solutions. | 1,369 |
 windsonr/vite-plugin-virtual-html | A plugin that enables more flexible and configurable HTML routing in Vite projects | 74 |
 bespoke-silicon-group/bsg_pipeclean_suite | A collection of Verilog designs for stress testing new CAD flows with increasing complexity | 10 |
 cambridgehackers/fpgamake | Generates Makefiles to synthesize and route digital circuits from Verilog designs using Vivado | 93 |
 yosyshq/nextpnr | A portable FPGA place and route tool with vendor-neutral timing-driven support for multiple FPGA families. | 1,332 |
 vlucas/bulletphp | A flexible PHP framework for building URL-based applications with functional-style routing | 417 |
 vanilla-icecream/vite-plugin-vue-routes | Provides file-based routing for Vue applications using Vite. | 1 |
 the-openroad-project/openroad | An RTL-to-GDSII flow tool for rapid semiconductor digital design | 1,660 |
 noaa-owp/t-route | A dynamic channel routing model that supports multiple network formulations and various routing solutions. | 44 |
 galacticstudios/kicadverilog | Converts KiCad schematic designs into Verilog code to simulate and design digital circuits | 57 |