basic_verilog

FPGA components

A collection of synthesizable Verilog SystemVerilog modules for FPGA projects.

Must-have verilog systemverilog modules

GitHub

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379 forks
Language: Verilog
last commit: 14 days ago
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alteradebouncedelayencoderfifofpgahlspwmspi-interfacespi-mastersynchronizertcluartuart-controlleruart-protocoluart-receiveruart-txuart-verilogverilogxilinx

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