basic_verilog
FPGA module library
A collection of synthesizable Verilog modules useful for FPGA projects
Must-have verilog systemverilog modules
2k stars
60 watching
383 forks
Language: Verilog
last commit: 4 months ago
Linked from 1 awesome list
alteradebouncedelayencoderfifofpgahlspwmspi-interfacespi-mastersynchronizertcluartuart-controlleruart-protocoluart-receiveruart-txuart-verilogverilogxilinx
Related projects:
| Repository | Description | Stars |
|---|---|---|
 alexforencich/verilog-pcie | A collection of Verilog modules implementing PCIe interfaces and bridges for various FPGAs | 1,162 |
 gmm-7550/gmm7550-hardware | A hardware development project that includes FPGA modules, adapter boards, and test systems for experimental electronics applications. | 19 |
 pwmarcz/fpga-tools | A collection of Verilog modules and tools for designing and working with FPGAs | 8 |
 pascalkuthe/openvaf | A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code. | 132 |
 aolofsson/oh | A comprehensive Verilog library of silicon-proven hardware building blocks for designing ASICs and FPGAs. | 1,206 |
 dawsonjon/fpu | A synthesizable IEEE 754 floating point library in Verilog. | 538 |
 pulp-platform/common_cells | A collection of reusable Verilog systemVerilog modules used to synchronize clocks and handles asynchronous crossings in digital circuits | 531 |
 pezy-computing/pzbcm | A collection of basic building blocks for designing digital systems in SystemVerilog | 34 |
 cornell-brg/pymtl3-net | Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design | 43 |
 chipsalliance/surelog | Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing | 373 |
| alexforencich/verilog-axis | Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs. | 750 |
 vlsi-eda/poc | Provides VHDL implementations of common hardware functions and a Python-based infrastructure for simulation and synthesis. | 554 |
 zipcpu/autofpga | Automates the process of creating and updating FPGA designs from peripherals in multiple languages. | 170 |
| alexforencich/verilog-uart | A Verilog implementation of a basic UART (Universal Asynchronous Receiver-Transmitter) to AXI Stream interface. | 427 |
 bensampson5/libsv | A SystemVerilog digital hardware IP library with automated testbenches and continuous integration | 23 |