open-register-design-tool
Register generator
Automates IC register definition and documentation
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
194 stars
44 watching
70 forks
Language: Verilog
last commit: about 1 year ago
Linked from 1 awesome list
asicedafpgajspecregister-descriptionsregisterssystemrdlsystemrdl-compilersystemveriloguvm
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