HLS
Digital circuit design toolset
A collection of tools and code for designing and implementing digital circuits using high-level synthesis
Vitis HLS LLVM source code and examples
380 stars
19 watching
58 forks
last commit: 5 months ago
Linked from 1 awesome list
Related projects:
Repository | Description | Stars |
---|---|---|
| A set of build rules and tools for synthesizing digital circuit designs from hardware description languages (HDLs) into usable ASIC chips. | 121 |
| A SystemC/C++ library of commonly-used hardware functions and components for High-Level Synthesis | 261 |
| Analog Devices Inc. provides reference designs and HDL libraries for various FPGA projects | 1,536 |
| Asynchronous circuit design and simulation tools using a hardware description language. | 102 |
| A modular hardware abstraction library for designing and implementing complex digital systems | 23 |
| Provides a format and tools for creating graphical representations of electronic circuits using SVG images | 14 |
| A high-level synthesis tool using LLVM to automatically generate digital circuit designs from C++ code | 118 |
| Generates Makefiles to synthesize and route digital circuits from Verilog designs using Vivado | 93 |
| A tool for formally verifying high-level synthesis of digital circuits | 88 |
| Designs and deploys neural networks integrated with Xilinx FPGAs for high-throughput applications | 83 |
| A collection of reusable Verilog systemVerilog modules used to synchronize clocks and handles asynchronous crossings in digital circuits | 531 |
| A tool for creating and displaying diagrams of digital circuits using a simple JavaScript API. | 73 |
| An intermediate representation language and simulator for digital circuit descriptions, aiming to simplify the development of EDA tools. | 397 |
| A collection of MyHDL cores and tools for complex digital circuit design | 85 |
| The NVDLA project provides hardware designs and tools for building deep learning inference accelerators. | 1,763 |