bazel_rules_hdl
by hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
AI summary
Circuit synthesis toolset
A set of build rules and tools for synthesizing digital circuit designs from hardware description languages (HDLs) into usable ASIC chips.
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