bazel_rules_hdl
Circuit synthesis toolset
A set of build rules and tools for synthesizing digital circuit designs from hardware description languages (HDLs) into usable ASIC chips.
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
121 stars
17 watching
45 forks
Language: Starlark
last commit: almost 2 years agoLinked from 1 awesome list
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