fusesoc
Circuit builder
A toolset for managing and building digital circuit designs using hardware description languages like Verilog or VHDL
Package manager and build abstraction tool for FPGA/ASIC development
1k stars
65 watching
248 forks
Language: Python
last commit: 11 months ago
Linked from 5 awesome lists
edafpgapackage-managerpythonreuseverilogvhdl
ly0n/awesome-robotic-tooling
ben-marshall/awesome-open-hardware-verification
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