chisel
Circuit generator
A hardware design language that allows software developers to describe digital electronics and circuits in a programming language, facilitating the creation of reusable components and libraries.
Chisel: A Modern Hardware Design Language
4k stars
150 watching
600 forks
Language: Scala
last commit: about 18 hours ago
Linked from 2 awesome lists
chip-generatorchiselchisel3firrtlrtlscalaverilog
aolofsson/awesome-opensource-hardware
drom/awesome-hdlRelated projects:
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|---|---|---|
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| chipsalliance/surelog | Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing | 369 |
 siliconcompiler/lambdalib | A modular hardware abstraction library for designing and implementing complex digital systems | 23 |
 tcr/hoodlum | A Rust-based HDL compiler targeting FPGA design and development | 97 |
| chipsalliance/verible | Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. | 1,384 |
 sylefeb/silice | A hardware description language that simplifies designing parallel and pipelined algorithms into FPGA hardware | 1,304 |
 conal/talk-2015-haskell-to-hardware | A compiler project that translates Haskell programs to hardware instructions for parallel processing on reprogrammable devices. | 58 |
 terostechnology/vscode-teroshdl | An integrated development environment plugin for HDL designers and developers. | 571 |
| chipsalliance/synlig | A SystemVerilog synthesis tool that generates digital circuit designs from HDL code | 170 |
 xilinx/hls | A collection of tools and code for designing and implementing digital circuits using high-level synthesis | 379 |
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