chiselverify
Verification tool
A verification library for digital hardware described in Chisel or legacy components from VHDL, Verilog, or SystemVerilog
A dynamic verification library for Chisel.
142 stars
12 watching
23 forks
Language: Scala
last commit: over 1 year ago
Linked from 1 awesome list
bus-functional-modelchiselchisel-testconstrained-random-verificationcoveragefunctional-coveragescalatestingtimed-assertionsverification
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