Cores-VeeR-EL2

RISC-V processor core

A Verilog RTL design for an EL2 RISC-V core with various peripherals and features

VeeR EL2 Core

GitHub

250 stars
27 watching
75 forks
Language: SystemVerilog
last commit: 4 days ago
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ahb-liteasic-designaxi4el2fpgafusesocopen-source-hardwareprocessorrisc-vriscvriscv32rtlverilatorwestern-digital

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