muntjac
RISC-V processor
A minimal 64-bit RISC-V multicore processor designed to be easy to understand and extend for educational and academic purposes.
64-bit multicore Linux-capable RISC-V processor
79 stars
12 watching
10 forks
Language: SystemVerilog
last commit: 5 months ago
Linked from 1 awesome list
aolofsson/awesome-opensource-hardwareRelated projects:
| Repository | Description | Stars |
|---|---|---|
| lowrisc/ibex | A 32-bit RISC-V CPU core designed for embedded control applications with configurable extensions and parameters. | 1,407 |
 b224hisl/rioschip | A small RISC-V core designed to support out-of-order execution and double issue architecture for efficient instruction processing. | 33 |
 gsmecher/minimax | An experimental RISC-V CPU implementation designed to optimize performance by executing compressed instructions first and using a microcoded instruction path | 205 |
 black-parrot/black-parrot | A Linux-capable RISC-V multicore accelerator designed to be small, modular, and easy to use for various applications. | 634 |
 moonbaseotago/vroom | An open-source RISC-V CPU implementation with high performance and multithreading capabilities. | 481 |
 olofk/serv | An award-winning RISC-V CPU designed for low-power and area-efficient designs | 1,457 |
 riscv-mcu/riscv-openocd | A fork of OpenOCD with RISC-V microcontroller support | 35 |
 rust-embedded/riscv | Provides low-level access and interfaces for writing software on RISC-V microcontrollers. | 874 |
 riscv-rust/gd32vf103xx-hal | A hardware abstraction layer for the GD32VF103 microcontroller family | 54 |
| riscv-rust/gd32vf103-pac | A peripheral access crate for a specific microcontroller family | 36 |
 mrlsd/riscv-fs | A F# implementation of the RISC-V Instruction Set Architecture | 282 |
 risc0/risc0 | A platform for executing and verifying computations in a secure, programmable virtual machine. | 1,731 |
 riscv/sail-riscv | A comprehensive formal specification of a RISC-V processor architecture using the Sail language | 480 |
 lekkit/rvvm | An emulator and virtual machine for the RISC-V instruction set architecture. | 953 |
 mariusmm/risc-v-tlm | A RISC-V processor simulator with SystemC and TLM-2 support for various instruction sets and peripherals. | 285 |