basic_verilog

alexforencich/verilog-pcie1.2K

PCIe interface libraries

A collection of Verilog modules implementing PCIe interfaces and bridges for various FPGAs

gmm-7550/gmm7550-hardware19

FPGA modules

A hardware development project that includes FPGA modules, adapter boards, and test systems for experimental electronics applications.

pwmarcz/fpga-tools8

FPGA toolkit

A collection of Verilog modules and tools for designing and working with FPGAs

pascalkuthe/openvaf132

Verilog-A compiler

A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code.

aolofsson/oh1.2K

ASIC/FPGA library

A comprehensive Verilog library of silicon-proven hardware building blocks for designing ASICs and FPGAs.

dawsonjon/fpu538

Floating point library

A synthesizable IEEE 754 floating point library in Verilog.

pulp-platform/common_cells531

Clock synchronizer modules

A collection of reusable Verilog systemVerilog modules used to synchronize clocks and handles asynchronous crossings in digital circuits

pezy-computing/pzbcm34

Digital system components

A collection of basic building blocks for designing digital systems in SystemVerilog

cornell-brg/pymtl3-net43

OCN generator

Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design

chipsalliance/surelog373

SystemVerilog processor

Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing

alexforencich/verilog-axis750

AXI bus components

Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs.

vlsi-eda/poc554

Hardware library

Provides VHDL implementations of common hardware functions and a Python-based infrastructure for simulation and synthesis.

zipcpu/autofpga170

FPGA designer

Automates the process of creating and updating FPGA designs from peripherals in multiple languages.

alexforencich/verilog-uart427

UART IP core

A Verilog implementation of a basic UART (Universal Asynchronous Receiver-Transmitter) to AXI Stream interface.

bensampson5/libsv23

HDL library

A SystemVerilog digital hardware IP library with automated testbenches and continuous integration