public

Hardware generator

Translates ONNX models to Verilog-based hardware implementations

GitHub
51 stars
2 watching
11 forks
Language: Verilog
last commit: 10 months ago
Linked from 1 awesome list


Backlinks from these awesome lists:

Related projects:

Repository Description Stars
pyhdi/veriloggen A framework that allows designing hardware using Python, providing high-level abstractions for efficient domain-specific languages and tools. 306
chipsalliance/uhdm Generates C++ implementation of the SystemVerilog Object Model and related tools based on YAML descriptions 202
nvlabs/verilog-eval An evaluation harness for generating Verilog code from natural language prompts 179
cornell-brg/pymtl3-net Generates synthesizable Verilog for on-chip networks with customizable parameters and modular design 43
pascalkuthe/openvaf A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code. 129
nic30/hwt A toolset for generating and simulating hardware designs with Python 202
chipsalliance/aib-phy-hardware Hardware implementation of an interface bus specification 127
pyhdi/pyverilog Toolkit for analyzing and processing Verilog HDL designs 640
nic30/hdlconvertor An ANTLR4-based parser and code generator for SystemVerilog/VHDL 280
zachjs/sv2v Converts SystemVerilog to Verilog code for hardware design and simulation 561
takenobu-hs/haskell-ethereum-assembly A Haskell-based DSL for generating Ethereum Virtual Machine (EVM) bytecode 66
interplanetary-robot/verilog.jl A Verilog generation DSL for Julia. 48
cornell-brg/pymtl A Python-based framework for building and testing hierarchical hardware models at multiple levels of abstraction. 237
chipsalliance/surelog Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing 367
chipsalliance/verible Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. 1,380