cva6
RISC-V CPU
A 6-stage RISC-V CPU designed to boot Linux and support Unix-like operating systems
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
2k stars
93 watching
702 forks
Language: Assembly
last commit: 2 months ago
Linked from 1 awesome list
arianeasiccpufpgarisc-vrv64gcsystemverilog-hdl
Related projects:
Repository | Description | Stars |
---|---|---|
| A 32-bit RISC-V CPU core with a two-stage pipeline designed for low-cost embedded control applications. | 29 |
| A configurable RISC-V processor core with various extensions and peripherals | 282 |
| A 4-stage RISC-V core for compute-intensive applications with a general-purpose extension interface | 225 |
| A secure, 4-stage RISC-V core designed for high-security applications with both machine mode and user mode capabilities | 133 |
| Functional verification project for RISC-V cores | 458 |
| Develops standards for launching and managing application containers across different platforms | 3,247 |
| A bootloader and development SDK providing a set of libraries and tools for building UEFI firmware | 13,527 |
| A RISC-V processor core design implemented in SystemVerilog RTL | 830 |
| A set of libraries and data structures designed to simplify the development of high-performance concurrent systems in C. | 2,409 |
| A CLI tool for spawning and running containers on Linux according to the OCI specification | 11,987 |
| A flexible and parameterizable floating-point unit design for RISC-V processors | 440 |
| High-quality implementations of reinforcement learning algorithms for research and development purposes | 15,885 |
| Tool for building and managing PKI CAs using a shell-based utility | 4,088 |
| An application kernel that provides isolation between running applications and the host operating system | 15,931 |
| Generates RISC-V instruction sequences for test verification and modeling | 268 |