chisel
Circuit generator
A hardware design language that allows software developers to describe digital electronics and circuits in a programming language, facilitating the creation of reusable components and libraries.
Chisel: A Modern Hardware Design Language
4k stars
153 watching
604 forks
Language: Scala
last commit: 11 months ago
Linked from 2 awesome lists
chip-generatorchiselchisel3firrtlrtlscalaverilog
aolofsson/awesome-opensource-hardware
drom/awesome-hdlRelated projects:
| Repository | Description | Stars |
|---|---|---|
 chiselverify/chiselverify | A verification library for digital hardware described in Chisel or legacy components from VHDL, Verilog, or SystemVerilog | 142 |
 facebook/chisel | A collection of LLDB commands to assist debugging iOS apps. | 9,130 |
 jpillora/chisel | A fast TCP/UDP tunnel over HTTP secured via SSH | 13,747 |
 clash-lang/clash-compiler | A Haskell-based compiler for hardware description languages like VHDL, Verilog, and SystemVerilog. | 1,451 |
 hdl/bazel_rules_hdl | A set of build rules and tools for synthesizing digital circuit designs from hardware description languages (HDLs) into usable ASIC chips. | 121 |
| chipsalliance/surelog | Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing | 373 |
 siliconcompiler/lambdalib | A modular hardware abstraction library for designing and implementing complex digital systems | 23 |
 tcr/hoodlum | A Rust-based HDL compiler targeting FPGA design and development | 97 |
| chipsalliance/verible | Develops a system for parsing and analyzing SystemVerilog code to improve developer productivity and ensure style compliance. | 1,403 |
 sylefeb/silice | A hardware description language that simplifies designing parallel and pipelined algorithms into FPGA hardware | 1,326 |
 conal/talk-2015-haskell-to-hardware | A compiler project that translates Haskell programs to hardware instructions for parallel processing on reprogrammable devices. | 58 |
 terostechnology/vscode-teroshdl | A suite of tools and plugins for HDL developers to simplify development, testing, and maintenance of digital circuits. | 580 |
| chipsalliance/synlig | A SystemVerilog synthesis tool that generates digital circuit designs from HDL code | 170 |
 xilinx/hls | A collection of tools and code for designing and implementing digital circuits using high-level synthesis | 380 |
 devbisme/skidl | A Python package that compactly describes electronic circuits and components. | 1,069 |