verilog-wishbone
Wishbone components
Components for building Wishbone bus systems with flexible interfaces and parametrization.
Verilog wishbone components
109 stars
16 watching
30 forks
Language: Python
last commit: almost 2 years ago
Linked from 1 awesome list
Related projects:
| Repository | Description | Stars |
|---|---|---|
| | Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs. | 750 |
| | A collection of Verilog modules implementing PCIe interfaces and bridges for various FPGAs | 1,162 |
| | An FPGA implementation of an I2C interface with various slave and master interfaces. | 557 |
| | A Verilog implementation of a basic UART (Universal Asynchronous Receiver-Transmitter) to AXI Stream interface. | 427 |
| | A parametrizable combinatorial LFSR/CRC module with various wrappers for different applications | 138 |
| | Hardware implementation of an interface bus specification | 128 |
| | Provides Ethernet interface modules for Cocotb simulation | 56 |
| | AXI interface modules for Cocotb simulation models | 219 |
| | A collection of reusable hardware components with accompanying assets and metadata | 23 |
| | An open-source Verilog project providing optimized bus bridges and components for high-performance interconnects. | 496 |
| | A comprehensive Verilog library of silicon-proven hardware building blocks for designing ASICs and FPGAs. | 1,206 |
| | Provides a set of APIs and protocols for interacting with WIZnet TCP/IP chips | 2 |
| | A package to build and flash MicroPython firmware for various ESP32 boards | 0 |
| | An open-source simulation framework for PCI express systems. | 141 |
| | Automates the process of creating and updating FPGA designs from peripherals in multiple languages. | 170 |