wb2axip
Bus bridges
An open-source Verilog project providing optimized bus bridges and components for high-performance interconnects.
Bus bridges and other odds and ends
489 stars
31 watching
101 forks
Language: Verilog
last commit: 11 months ago
Linked from 1 awesome list
axi-busfpgagplv3wishbonewishbone-busxilinxxilinx-vivado
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