ddr5_phy

DDR5 PHY verification

Verification of a digital data-path in a DDR5 Physical Layer

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

GitHub

42 stars
2 watching
22 forks
Language: SystemVerilog
last commit: 8 months ago
Linked from 1 awesome list

gpsystemveriloguvm

Backlinks from these awesome lists:

Related projects:

Repository Description Stars
waviousllc/wav-lpddr-hw A hardware design for a scalable DDR PHY IP that supports multiple DRAM protocols and integrates a microcontroller unit. 98
yosyshq/sby A front-end driver program for Yosys-based formal hardware verification flows 406
tpoikela/uvm-python Port of the SystemVerilog Universal Verification Methodology to Python 243
pezy-computing/pzbcm A collection of basic building blocks for designing digital systems in SystemVerilog 34
openhwgroup/core-v-verif Functional verification project for RISC-V cores 446
bespoke-silicon-group/bsg_ddr3_io Designs and automates simulation of a DDR3 interface for a specific IC process 4
osvvm/osvvm A comprehensive VHDL verification utility library with advanced testing and verification capabilities 225
raysalemi/uvmprimer Compiled and simulated UVM Primer book examples for easy testing and learning 483
bensampson5/libsv A SystemVerilog digital hardware IP library with automated testbenches and continuous integration 23
pyuvm/pyuvm An implementation of the IEEE Standard for Universal Verification Methodology in Python 372
pyhdi/pyverilog Toolkit for analyzing and processing Verilog HDL designs 640
chipsalliance/surelog Provides a comprehensive front-end for SystemVerilog 2017 design and testbench processing 367
mit-pdos/perennial A system for verifying correctness of concurrent and crash-safe systems with recovery procedures 163
sifive/prockami Formal verification and implementation of RISC-V processor designs using Coq. 22
sgherbst/svreal A synthesizable real number library in SystemVerilog, supporting both fixed-point and floating-point formats for digital design. 43