axi

AXI network components

Provides reusable IP modules and verification infrastructure for designing high-performance on-chip communication networks adhering to AXI standards.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

GitHub

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271 forks
Language: SystemVerilog
last commit: almost 2 years ago
Linked from 2 awesome lists

asicaxiaxi4axi4-litefpgahardwareipnetwork-on-chiprtlsystemverilog

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