RPHAX
Hardware accelerator prototyper
An automation framework to quickly prototype and integrate hardware accelerators on Xilinx FPGAs
RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and create a Zynq based block design.
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Language: Tcl
last commit: almost 2 years ago
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