core_axi_cache

ultraembedded/core_jpeg216

JPEG decoder

A Verilog implementation of a high-performance JPEG decoder core for FPGA-based video playback systems

ultraembedded/core_ddr3_controller375

DDR3 controller

A lightweight AXI-4 DDR3 controller designed to run at reduced clock speeds, simplifying the interface with FPGAs.

long2ice/fastapi-cache1.4K

Cache

Caches FastAPI responses and function results with support for multiple backends

zeroasiccorp/umi142

Memory Interface

Defines a standard interface for accessing memory through request-response transactions.

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

alexforencich/verilog-uart427

UART IP core

A Verilog implementation of a basic UART (Universal Asynchronous Receiver-Transmitter) to AXI Stream interface.

al8n/stretto412

Cache library

A high-performance, thread-safe cache implementation for Rust.

chipsalliance/cores-veer-el2252

RISC-V processor core

A Verilog RTL design for an EL2 RISC-V core with various peripherals and features

alexforencich/verilog-axis750

AXI bus components

Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs.

arago/lru_cache36

LRU Cache

A cache implementation using an LRU (Least Recently Used) eviction strategy and ETS tables for efficient storage and retrieval of cached data.

taichi-ishitani/tvip-axi363

AXI VIP

An AMBA AXI4 VIP implementation in SystemVerilog

256dpi/arduino-mqtt1K

MQTT client

An MQTT client library for Arduino

sasa1977/con_cache911

Cache

An Elixir-based key/value cache with row-level isolated writes and time-to-live (TTL) support.

abouvier/slim-redis-cache17

Caching middleware

A Redis-based caching middleware for the Slim PHP framework

stnolting/neorv321.6K

Embedded processor

An open source 32-bit RISC-V CPU and microcontroller-like SoC written in VHDL for customizable embedded systems