core_axi_cache
AXI cache
A Verilog implementation of a 128KB AXI cache with limited pseudo-random replacement and write-back architecture
128KB AXI cache (32-bit in, 256-bit out)
44 stars
4 watching
5 forks
Language: Verilog
last commit: over 3 years ago
Linked from 1 awesome list
aolofsson/awesome-opensource-hardwareRelated projects:
| Repository | Description | Stars |
|---|---|---|
| ultraembedded/core_jpeg | A Verilog implementation of a high-performance JPEG decoder core for FPGA-based video playback systems | 212 |
| ultraembedded/core_ddr3_controller | A lightweight AXI-4 DDR3 controller designed to run at reduced clock speeds, simplifying the interface with FPGAs. | 370 |
 long2ice/fastapi-cache | Caches FastAPI responses and function results with support for multiple backends | 1,366 |
 zeroasiccorp/umi | Defines a standard interface for accessing memory through request-response transactions. | 142 |
 chipsalliance/cores-veer-eh1 | A RISC-V processor core design implemented in SystemVerilog RTL | 822 |
 alexforencich/verilog-uart | A Verilog implementation of a basic UART (Universal Asynchronous Receiver-Transmitter) to AXI Stream interface. | 424 |
 al8n/stretto | A high-performance, thread-safe cache implementation for Rust. | 412 |
| chipsalliance/cores-veer-el2 | A Verilog RTL design for an EL2 RISC-V core with various peripherals and features | 250 |
| alexforencich/verilog-axis | Provides a collection of Verilog modules and wrappers for designing AXI stream bus components in FPGAs. | 746 |
 arago/lru_cache | A cache implementation using an LRU (Least Recently Used) eviction strategy and ETS tables for efficient storage and retrieval of cached data. | 36 |
 taichi-ishitani/tvip-axi | An AMBA AXI4 VIP implementation in SystemVerilog | 363 |
 256dpi/arduino-mqtt | An MQTT client library for Arduino | 1,027 |
 sasa1977/con_cache | An Elixir-based key/value cache with row-level isolated writes and time-to-live (TTL) support. | 910 |
 abouvier/slim-redis-cache | A Redis-based caching middleware for the Slim PHP framework | 17 |
 stnolting/neorv32 | An open source 32-bit RISC-V CPU and microcontroller-like SoC written in VHDL for customizable embedded systems | 1,602 |