core_ddr3_controller
DDR3 controller
A lightweight AXI-4 DDR3 controller designed to run at reduced clock speeds, simplifying the interface with FPGAs.
A DDR3 memory controller in Verilog for various FPGAs
366 stars
19 watching
86 forks
Language: Verilog
last commit: about 3 years ago
Linked from 1 awesome list
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