riscv-fs

mariusmm/risc-v-tlm285

RISC-V simulator

A RISC-V processor simulator with SystemC and TLM-2 support for various instruction sets and peripherals.

ronsor/riscv-zig48

CPU emulator

A RISC-V CPU emulator written in Zig.

riscv-mcu/riscv-openocd35

RISC-V debugger

A fork of OpenOCD with RISC-V microcontroller support

chipsalliance/riscv-dv1K

RISC-V simulator

An instruction generator for RISC-V processor verification

mit-plv/riscv-semantics159

RISC-V semantics

A formal specification of the RISC-V instruction set architecture in Haskell

lekkit/rvvm953

RISC-V VM

An emulator and virtual machine for the RISC-V instruction set architecture.

riscv/sail-riscv480

RISC-V spec

A comprehensive formal specification of a RISC-V processor architecture using the Sail language

lucasgleba/zkriscv47

ZK CPU emulator

A RISC-V CPU emulator implemented as a zero-knowledge verification system to prove program execution correctness

chipsalliance/cores-veer-eh1830

RISC-V Core

A RISC-V processor core design implemented in SystemVerilog RTL

mit-plv/riscv-coq110

RISC-V spec

An implementation of the RISC-V instruction set specification in Coq

riscv-rust/gd32vf103xx-hal54

Microcontroller HAL

A hardware abstraction layer for the GD32VF103 microcontroller family

olofk/serv1.5K

RISC-V CPU

An award-winning RISC-V CPU designed for low-power and area-efficient designs

lowrisc/muntjac79

RISC-V processor

A minimal 64-bit RISC-V multicore processor designed to be easy to understand and extend for educational and academic purposes.

fsharp/emacs-fsharp-mode209

F# IDE

Provides support and tools for the F# programming language within the Emacs text editor.

sifive/prockami22

Processor simulator

Formal verification and implementation of RISC-V processor designs using Coq.