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OpenLane | | | end to end ASIC flow |
OpenROAD | | | provides many of the tools in OpenLane |
Silicon Compiler | | | end to end ASIC flow |
Coriolis 2 | | | end to end ASIC flow |
OSS Cad Suite | 799 | 9 days ago | lots of open source tools useful for digital design |
OSFPGA | | | end to end FPGA flow with open source tools such as Yosys, VTR and VPR |
VHDL support - with GHDL | | | |
Awesome list of verification tools | 247 | over 2 years ago | |
Awesome list of HDL tools / libraries / cores ... | | | |
SemiWiki's list of open EDA tools | | | |
Andreas' list of awesome hardware tools | 1,874 | about 1 month ago | |
Awesome open source ASIC resources / High level synthesis (HLS) |
Amaranth | | | |
XLS | | | |
Spinal | 1,632 | 2 days ago | |
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Magic | | | old school, layout drawing tool; still a requirement in the modern flows. |
Klayout | | | modern style layout drawing tool |
Xschem | | | old school, schematic capture |
Mosaic | | | schematic capture (experimental) |
Ngspice | | | simulation |
Xyce | | | simulation |
gdsfactory | | | EDA tool to Layout and simulate Integrated Circuits |
Awesome open source ASIC resources / Generators |
OpenRAM | | | SRAM generator |
DFFRAM | 130 | 4 months ago | Memory Compiler using FF/Latch cells |
OpenFASoC | 233 | 2 days ago | Analogue IP generator (LDO, temperature sense etc) |
MOSAIC_BAG2 | | | Analogue IP generator framework (w/minimum working example) |
RgGen | 319 | 3 months ago | CSR generator (SystemVerilog/Verilog/VHDL RTL, UVM reg model etc) |
Awesome open source ASIC resources / PDK |
Sky130 | | | |
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Skywater PDK Slack | | | |
Twitter list | | | |
Awesome open source ASIC resources / Videos |
https://www.youtube.com/zerotoasic | | | Zero to ASIC course videos, interviews, news |
https://www.youtube.com/watch?v=OmEbzRp_NGg | | | Asianometry - the promise of open source EDA tools |
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Quickstart guide | | | |
join the community slack | | | Then #shuttle & #caravel channels |
FAQ | | | Check the |
https://platform.efabless.com/projects/public | | | See the projects submitted here: |
Awesome open source ASIC resources / Conferences |
The open source digital design conference | | | |
https://www.youtube.com/playlist?list=PLyynFETmdQDQdLCIu_HJBFNY17AAFp5W7 | | | OpenTapeout |
https://www.fossi-foundation.org/events | | | FOSSi events: |
https://wiki.f-si.org/index.php/FSiC2022 | | | Free silicon conference: |
Awesome open source ASIC resources / Courses |
Zero To ASIC course | | | |
VSD VLSI courses on Udemy | | | |
Awesome open source ASIC resources / Articles |
https://www.theregister.com/2020/07/03/open_chip_hardware/ | | | |
http://olofkindgren.blogspot.com/2019/12/2019-year-of-risc-v-and-open-source.html | | | |
https://zerotoasiccourse.com/post/ | | | |
Awesome open source ASIC resources / Mailing lists / newsletters |
https://medium.com/librecores/el-correo-libre-issue-46-11028b1d0e63#ead0 | | | El correo libre: |
https://zerotoasiccourse.com/newsletter/ | | | |
Awesome open source ASIC resources / Interest groups |
FOSSi | | | FOSSi Foundation is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems |
Chips Alliance | | | CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development |
WOSET | | | The WOSET workshop aims to galvanize the open-source EDA movement |
Awesome open source ASIC resources / Companies |
ChipFlow | | | Helping product companies to make their own chips with open source tools |
Efabless | | | simplifying chip creation |
LibreSilicon | | | open source manufacturing process standard |
LowRISC | | | open source silicon designs and tools |
Skywater Technology | | | foundry that first published open source PDK |
OpenHW Group | | | open-source cores, verification, software and standards |
YosysHQ | | | open source EDA & Formal Verification |
ZeroASIC | | | makers of silicon compiler ASIC tool flow |
Awesome open source ASIC resources / Work in progress |
Luna PnR | | | |