awesome-opensource-asic-resources

end to end ASIC flow

provides many of the tools in OpenLane

end to end ASIC flow

end to end ASIC flow

OSS Cad Suite

lots of open source tools useful for digital design

end to end FPGA flow with open source tools such as Yosys, VTR and VPR

old school, layout drawing tool; still a requirement in the modern flows.

modern style layout drawing tool

old school, schematic capture

schematic capture (experimental)

simulation

simulation

EDA tool to Layout and simulate Integrated Circuits

SRAM generator

DFFRAM

Memory Compiler using FF/Latch cells

OpenFASoC

Analogue IP generator (LDO, temperature sense etc)

Analogue IP generator framework (w/minimum working example)

RgGen

CSR generator (SystemVerilog/Verilog/VHDL RTL, UVM reg model etc)

Zero to ASIC course videos, interviews, news

Asianometry - the promise of open source EDA tools

Then #shuttle & #caravel channels

Check the

See the projects submitted here:

OpenTapeout

FOSSi events:

Free silicon conference:

El correo libre:

FOSSi Foundation is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems

CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development

The WOSET workshop aims to galvanize the open-source EDA movement

Helping product companies to make their own chips with open source tools

simplifying chip creation

open source manufacturing process standard

open source silicon designs and tools

foundry that first published open source PDK

open-source cores, verification, software and standards

open source EDA & Formal Verification

makers of silicon compiler ASIC tool flow