verilog-eval

nickg/nvc641

VHDL simulator

A VHDL compiler and simulator that translates VHDL code into native machine code for simulation purposes.

verigood-ml/public52

Hardware generator

Translates ONNX models to Verilog-based hardware implementations

zachjs/sv2v571

design converter

Converts SystemVerilog to Verilog code for hardware design and simulation

maluuba/nlg-eval1.4K

Model evaluator

A toolset for evaluating and comparing natural language generation models

galacticstudios/kicadverilog57

Circuit simulator

Converts KiCad schematic designs into Verilog code to simulate and design digital circuits

eirikpre/vscode-systemverilog130

SystemVerilog editor

A VS Code extension providing support for SystemVerilog code editing and analysis

pascalkuthe/openvaf132

Verilog-A compiler

A Verilog-A compiler built with Rust to compile circuit simulator models into efficient and high-quality code.

nvlabs/circuitops72

Data generation framework

A software framework providing a data infrastructure for generating datasets and deploying generative AI models in circuit optimization tasks.

cvlab-columbia/viper1.7K

Code generator

A framework for generating and executing Python code to solve visual inference tasks using large language models

olical/conjure1.8K

Code evaluator

An interactive environment for evaluating code within a running program.

interplanetary-robot/verilog.jl48

Verilog generator

A Verilog generation DSL for Julia.

nvlabs/edm1.4K

Generative model framework

This project provides a set of tools and techniques to design and improve diffusion-based generative models.

chipsalliance/sv-tests302

SystemVerilog tester

A comprehensive test suite for SystemVerilog standard compliance across various Verilog tools.

nic30/hdlconvertor284

VHDL/Verilog parser

An ANTLR4-based parser and code generator for SystemVerilog/VHDL

pyhdi/pyverilog645

HDL analyzer

Toolkit for analyzing and processing Verilog HDL designs